using the ADE. Additional Setup Required for EMIR Analysis. is the first blog in this series that takes you through the steps required to perform EMIR analysis in ADE using Spectre APS. % Add other model files if needed. From the ADE go to Setup !Model Libraries.. Choose menu item Tools->Corners (the Corners Setup window appears) 3. The most common EMIR analysis approach is to perform IR drop analysis on power nets and EM current analysis on power and signal nets. Optimizer is available only in ADE-GXL. I like the teacher presenting very clearly. However, before including the DSPF file in the simulation, it is recommended that you run the spfchecker utility on the DSPF file to ensure that the DSPF file is free of errors. As an analog or mixed-signal designer, you would be using Spectre APS in the Virtuoso Analog Design Environment (ADE) for block-level designs. If the technology file (most common format: ICT) is provided by the foundry and includes the current limits for the EM current analysis, you can include this file in EMIR simulation. This tutorial explains necessary steps required in preparing your design and using ADE to simulate the circuit. For more details on the advanced features or accuracy/performance optimization, refer to the following: For more information on Cadence products and services, visit www.cadence.com. Lately, you might have seen a need for analysing IR drop and EM currents, and you wonder which Cadence tool to use for analyzing potential EMIR problems in your design. It may not display this or other websites correctly. Offering a full verification flow to our customers and partners that delivers the highest verification throughput in the industry. ", "I enjoyed learning this course. stream ", "The course was very beneficial for me. In this case, follow the appropriate simulation procedures introduced in this document. The related statement is added in the Summary Information section, when you click Add/Modify. endobj In this course, you use the Virtuoso ADE Explorer and Spectre Circuit Simulator to simulate analog circuits with Verilog-A models. Using expression entry: If you've labelled output in schematic as 'Vout', enter the expression as 'phaseMargin (VF ("/Vout"))' without single quotes. Select "Add specification" from the drop down list on the up right corner. You use the Real-Time Tuning assistant to dynamically update results in the ADE Explorer cockpit after a single simulation run. Repeat the above for all corner tests. For more information please visit: https://www.cadence.com/content/cadence-www/global/en_US/home/training/custom_ic_analogrfdesign.html The tutorial assumes that you have the inverter cell with Note: Assuming you've already run the simulation once. Use more rectangles to draw out the wires. Cadence system analysis solutions provide highly accurate electromagnetic extraction and simulation analysis to ensure your system works under wide-ranging operating conditions. Rename the added test to match corner simulation (Optional). It reuses the Spectre APS and ADE setup, and requires only a few minor additions for defining and enabling EMIR analysis. In this course, you set up and run simulations on analog designs and use design variables in your setup, sweep system parameters and run simulations on a single testbench, using Spectre as the simulator, and view results in the Virtuoso . The EMIR flow requires a DSPF file to be extracted for the block to be analyzed with EMIR. Post-layout simulation methods are 1. using generated netlist by calibre 2. add pex view. 1. Please follow the below steps and let me know if you can't get it. The spfchecker utility may also add a few additional options in the Summary Information section. Cadence digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets. Cadence Tutorial D: Design Variables and Parametric Analysis 4 Virtuoso setup . Cadence custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization. tutorial on montecarlo simulation. endobj You will get an email to confirm your subscription. Never heard about the second one. In addition to the parasitic R and C elements, and devices, such as MOSFET and BJT, the DSPF file contains layer, coordinate, and width/length/area information, which is required for EMIR analysis. (Type: mkdir cadence) 4) Navigate to the new directory. <>/XObject<>/ProcSet[/PDF/Text/ImageB/ImageC/ImageI] >>/MediaBox[ 0 0 612 792] /Contents 4 0 R/Group<>/Tabs/S/StructParents 0>> Never miss a story from Analog/Custom Design (Analog/Custom design). Cadence Support provides access to support resources including an extensive knowledge base, access to software updates for Cadence products, and the ability to interact with Cadence Customer Support. Analog Integrated Circuit (IC) Design, Layout and more, https://www.cadence.com/content/damanalog-rf-design/virtuoso-ade-explorer-ds.pdf, ADE L-Calibre-Map Schematic Nets to CalibreView Nets does not work, Hierarchy Editor does not work with ADE Assembler/Explorer, pin's name is not visible in cadence layout XL, ADE XL switch view list for simulating verilog functional code. To run the spfchecker utility: The errors, if any, are reported in the .dspf.chklog file. You will get an email to confirm your subscription. Well, you can use Spectre APS to do just that. ADE-XL (GXL) and ADE-Explorer (called as Maestro) are available in IC6 Virtuoso of Cadence. The Voltus-Fi XL/Spectre EMIR flow provides many advanced features, such as static EMIR, Static Power Grid Solver (SPGS) point-to-point resistance checking, power gate handling, signal net IR drop, differential IR drop, what-if analysis, and self-heating analysis. The earner can create maestro cellviews, run Spectre simulations and analyze the waveforms in ViVA XL. ADE -> Outputs -> Setup. In order to solve this problem, Cadence has introduced ADE XL, and OCEAN XL. The Spectre EMIR solution provides two methods for analyzing EMIR. For each pin, maximum, average, and RMS current are reported. Thank you for subscribing. <> About Press Copyright Contact us Creators Advertise Developers Terms Privacy Policy & Safety How YouTube works Test new features Press Copyright Contact us Creators . Verilog-A together with this course definitely opens the innovation box. For more information, refer to Voltus-Fi Custom Power Integrity Solution XL User Guide. 5- Types of OCEAN commands As already mentioned, you can generate a specific ocean command file using your ADE (Analog Affirma in Cadence). This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register. Online Course Cadence helps you get the most out of your investment in our technologies through a wide range of education offerings. For a better experience, please enable JavaScript in your browser before proceeding. Enter your email address in the Subscriptions box and click SUBSCRIBE NOW to receive notifications about our latestSpectre Tech Tipsposts. ", "The course was at my level. Spectre APS provides a powerful transistor-level EMIR solution that uses a patented technology and enables you to perform EMIR analysis with high accuracy. Make sure to connect the power nets to a DC voltage source to enable power net detection, and for obtaining the proper voltage reference for IR drop calculation. Cadence Cerebrus Intelligent Chip Explorer, Voltus-XFi Custom Power Integrity Solution, SI/PI Analysis Point Tools for IC Packaging, Advanced PCB Design & Analysis Resources Hub, Cadence Joint Enterprise Data and AI Platform, Custom IC / Analog / Microwave & RF Design Courses, Determine the importance of the top-down design methodology for accelerating complex system development, Write behavioral models of electrical circuits using the correct Verilog-A language and syntax, Create, edit, and simulate a variety of analog models written in the Verilog-A language using the Virtuoso ADE Explorer and the command-line environment, Verify that Verilog-A modules properly describe the intended function, Use software design tools to facilitate model development, Some programming, UNIX or Linux, a text editor. The layout view can be accessed by clicking Results - EM/IR Data - Layout Analysis. Finally, you examine the AHDL Linter feature to detect potential bugs in the Verilog-A codes. Click Add Model File . Alternatively, the IR drop and EM current information can be graphically displayed using Voltus-Fi XL in the layout environment. Length: 3 days (24 Hours) Digital Badge Available Course Description In this course, you use the Virtuoso ADE Explorer and Spectre Circuit Simulator to simulate analog circuits with Verilog-A models. The class schedule is intended to adequately cover all topics of the ADE course. endobj You use the Verilog-A syntax, structure Verilog-A modules, and generate symbols for your Verilog-A cells for use in a system hierarchy. You learn to use the Run Plan assistant in the ADE Assembler to create mini run plans to verify some of your design considerations. The Cadence EMIR solution is called Voltus-Fi XL, which uses Spectre EMIR as the simulation engine. Dec 13, 2017 #2 C CAMALEAO Full Member level 4 Joined Jul 29, 2016 Messages 201 Helped 2 2. Figure 4: Setting the width of a PMOS transistor to a passed parameter value called "pw". It is clear, well explained()and the labs are really good." 1) Log into a lab computer then log into LATS. dr.CkT?7K.Rx^DScue.C!Nh*$ 3w:f3+{d|H"GMY1_:RZ(1081HK-0iOJDSk"Io*Z|A6>jy!rGSIWB3:Pt&ZuxZkJ^!e| m&5\ PY^&6:d-PUwKLKh@c:q"h7%j!7OSqcB|: Q(x`xC8/0l3&+yIc= X$,Enm`BXko`Gm1>K!\z`_FnN|wy[ This is displayed in the Summary Information section at the bottom of the form. You are using an out of date browser. Subscribe for in-depth analysis and articles. The EMIR analysis options can be specified in the Spectre EMIR/Voltus-Fi XL Analysis Setup form, which can be opened by clicking Setup - EM/IR Analysis in Virtuoso ADE Explorer. After analyzing the yield view, filtering yield information for successfully completed points, you plot histograms and print statistical parameters. Select "Monte Carlo Sampling" Later go to the Corners set-up, as shown in the picture below, and choose the parameters you want to vary, Usually, the temperature and other parameters.In my case, I want variations on the temperature (-20-to+85C) and in VDD (the power supply from 1.1V to 1.3V). See how our customers create innovative products with Cadence. Open ADE Explorer and open or create a maestro view, as shown above 2. All customers with maintenance can have support.cadence.com access, including universities. JavaScript is disabled. Cadence claims that the integration of deep electromagnetic (EM) and thermal embedded analyses in the V16 release will lead to a 3X reduction in turnaround time (TAT). 4 0 obj -Online Course-, clear content, clear labs, () the trainer has achieved a very good performance with clear explanations, good timing between explanations vs. labs time (to fit everybody's level) and very good understanding of our expectations. what are the options available in monte carlos simulations. It's not a matter of "premium cadence users". The common simulation flow in circuit design requires you to first perform transient simulations on your pre-layout design. To set up the power net IR drop analysis: The analysis statement is added in the Summary Information section. All reported errors must be fixed; otherwise, you may spend hours in EMIR simulation just producing garbage. Hi Pancho. York EMIL Tutorial Series Tut #1 1 - 9 Figure 14: The ADE window.. longer supports Internet Explorer. ", "After this course I know how to improve my existent modules and () have several new concepts to implement using Verilog-A for memory compilers design needs and more. For instructions on how to log into the servers remotely using X2Go, and also a basic Virtuoso tutorial, see the Software section on the course website. This blog introduces you to the basic Spectre EMIR/Voltus-Fi XL flow for analyzing IR drop and EM currents in the Virtuoso ADE environment. They are very helpful for a fast startup in applying the methods.-Online Course-. Cadence trainings are always very professional and a good learning opportunity. ^kXo` sjjD 3) In your home directory, create a directory called Zcadence. Each module requires 1 to 2 hours to complete both the lecture presentation and the lab activity. An open IP platform for you to customize your app-driven SoC design. To include the DSPF file in the simulation: In the netlist, the file is included with a dspf_include statement. You also have an optional appendix which briefly covers Reliability Analysis. Cadence Virtuoso ADE Assembler is an advanced design and simulation environment that extends the capabilities of Virtuoso ADE Explorer, adding all the tests needed to fully verify a design over all operational, process, and environmental conditions. The content is written to the emir.conf file, which is included in the Spectre command line with the +emir command-line option, as shown below. Figure 15: The Model Library Setup window.. We will only highlight the absolute basics, study the Cadence manuals for more informa-tion. Browse Cadences latest on-demand sessions and upcoming events. The iterated method provides higher capacity/performance with minimal accuracy loss (<20% for the top IR drop and EM current values). ", "I especially liked the complete documentation and lab descriptions. Cadence Spectre(in MMSIM) // Spectre Simulation Setup. Next, create the in pin. In this session of video, I tell the post-layout simulation by three method and final tape out procedure. In Corners Setup window, choose menu item for Import Corners from PCF file. Cadence custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization. 3 0 obj It explains DC analysis and DC sweep in cadence with examles. You learn to use the Run Plan assistant in the ADE Assembler to create minirun plans to verify some of your design considerations. 1. By default, Dynamic (transient) EMIR analysis is selected in the form. If enabled, in addition to reporting the IR drop voltage and the EM current values, it compares the EM currents with the current limits per layer segment, and reports errors where the limit is exceeded. The reference voltage is the voltage of the connected voltage source. ADE, as well as enable the ability to do parametric analysis. <> 2) Open a terminal window. These new features are not the concern of this tutorial. Cadence digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets. This blog introduces you to EMIR analysis and focusses on the basic Spectre EMIR flow using the ADE environment. Processor design - Wikipedia Processor design is a subfield of computer engineering and electronics engineering (fabrication) that deals with creating a processor, a key component of computer hardware.. Regional course catalogs may be viewed here. You can then edit this file and add your own specific commands, to What's the difference to the adexl? lH48jxMw;l; Xqn Mvj0Z=)2)&cJp~{_ cU.5-V2F1*&8hk1~- } 2%O9k&uzkY`SzxM@|Jkc'A1$ZbC|A+EBBe'SCEe=6B*?L2a>A&P? Click Add Corner. 2022 Cadence Design Systems, Inc. All Rights Reserved. At the end of this, the gates should be connected, as shown below: Similarly, create a metal 1 wire (using rectangle) to connect the drains of the two transistors (connect the two vias, as shown below). 1. Click Import from Test. Length: 1/2 day (4 Hours) Digital Badge Available This course introduces you to the maestro cellview and the Virtuoso ADE Explorer tool that uses it. This section will guide you to run AC analysis and utilize Calculator in ADE. . Double click on the variable "Value" tab and click on the three dots button to bring up the "Parameterize" window. In this course, you set up a Monte Carlo run in ADE Explorer, accounting for mismatch variations and learn to autostop your run based on a target yield. Curious? 5.4.2 Cadence Spectre Simulation -1 // DC Analysis. Cadence system analysis solutions provide highly accurate electromagnetic extraction and simulation analysis to ensure your system works under wide-ranging operating conditions. Issued by Cadence Design Systems The earner of this badge can set up single and multiple tests in Virtuoso ADE Assembler. As such, each day covers 4 to 5 modules. To do this, click on the first icon (the icon shows a Folder with "CSV" written on it) and select the menu item If a technology file is provided, the current is compared with the given current limit for the layer segment, and a pass/fail result with percentage is reported. These options are recommended for better mapping between DSPF and schematic netlist. Virtuoso ADE Explorer, Assembler & Verifier by Cadence Education Services & Custom IC/Analog/RF. I liked that it was practical with exercises to test out what we learned. In addition to the regular ADE output, like voltage or current waveforms, EMIR simulation provides the following additional EMIR text reports: These reports can be accessed by clicking Results - EM/IR Data - Report in Virtuoso ADE Explorer. Watch on. Which do you use ? I like the compact way the topics are presented. f!q=)H3!4W201:PgR5LNQ/~(YC!Vb`IWE%F*gJmM3!eF@m(WVRN}7 ED+H/c$,|s5G4I,S_I.M1vy2o~doN-b#)q\Em-(j+QM[o#5!TepI]H?IsiFaB|(gf5D>@[}2M:f!md(9cX9u engineering, the cadence virtuoso ade explorer provides a new entry level cockpit to test a circuit early in the development cycle the tool supports schematic centric and specification See how our customers create innovative products with Cadence. The Spectre EMIR/Voltus-Fi XL flow provides many advanced features, such as static EMIR, Static Power Grid Solver (SPGS) point-to-point resistance checking, power gate handling, signal net IR drop, differential IR drop, what-if analysis, and self-heating . Analog/Custom Design (Analog/Custom design, Once the solver method is selected, the related statement is added in the. To include a technology file in the simulation: Once the DSPF file and EMIR configuration are set up, run the simulation in ADE Explorer. what it is ? To start simulation, choose Tools->Analog Environment from the top menu in Schematic Editing window, Analog Design Environment (ADE) will appear. Spectre Tech Tips: How to Perform EMIR Analysis in ADE Using, Spectre Classic Simulator, Spectre Accelerated Parallel Simulator (APS), and Spectre Extensive Partitioning Simulator (XPS) User Guide, IC6.1.7: Voltus-Fi EMIR Analysis Workshop- The DSPF flow (RAK). You use the Real-Time Tuning assistant to dynamically update results in the ADE Explorer cockpit after a single simulation run. Analog Design Environment (ADE) is integrated on Cadence Custom IC Design software. series of ADE 5.0. Cadence tutorial : DC analysis and DC sweep in cadence 47,768 views Aug 18, 2014 This is a very basic tutorial for beginners. EMIR analysis is just another step in this transient simulation flow. For each power net tap node, the IR drop voltage value is reported. 5.4.2 Cadence Spectre Simulation -2 // AC & Transient Analysis. For EM analysis setup, repeat the above steps, select the DSPF subcircuit instance instead of its terminals, and select the avg and rms options next to the EM Current Analysis field. First thing to do is make sure that the simulator has access to the needed transistor models. Regional course catalogs may be viewed here. To select a solver for EMIR analysis: Once the solver method is selected, the related statement is added in the Summary Information section. 2022 Cadence Design Systems, Inc. All Rights Reserved. Click section and set the desired corner for the model files. <>>> The second method is the iterated method that couples a linear solver for the parasitics with Spectre APS for circuit simulation. Once the layout is available, postlayout simulations are performed to check the impact of layout implementation. Thank you for subscribing. 5.4.2 Cadence Spectre Simulation -4 Cadence spectre MOS gm, ro Plot . VLIW or An open IP platform for you to customize your app-driven SoC design. For each net resistor segment, the average and RMS current are reported. The design process involves choosing an instruction set and a certain execution paradigm (e.g. There's a mechanism via the university program by which users can have access to a "light" account for support (which can access the documents, but can't log support requests; these have to go via one of the university contacts or in the case of the . Cadence PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow. You also have an optional appendix which briefly covers Reliability Analysis.This course is a part of the Virtuoso ADE Explorer and Assembler series: After completing this course, you will be able to: You must have experience with or knowledge of the following: Or you must have completed the following courses: Please see course learning maps at this link for a visual representation of courses and course relationships. Cadence PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow. 1 0 obj 5.4.2 Cadence Spectre Simulation -3 // Parametric Analysis & Multi-parameter Sweep. The earner can transistion between Assembler and Explorer and translate ADE-L and XL setups to the Assembler. Private classes taught at customer facilities may require adjustments or modifications to this schedule. In addition, Spectre EMIR analysis provides powerful options for optimizing EMIR accuracy and performance. Verilog-A is a high-level language that uses modules to describe the structure and behavior of analog systems and their components. "The possibilities of Verilog-A are really impressive, and I was not aware of them, even using spectre for several years., "To get a basic understanding, the course is good. CadenceLIVE Europe - November 21-22, 2022. After completing this course, you will be able to: You must have experience with or knowledge of the following: And experience with the following software: Please see course learning maps at this link for a visual representation of courses and course relationships. In the schematic window, select Launch/ADE XL, in the pop-up window, select the "Create new View" radio button, then press OK. Press OK again when the "Create new . How to Perform EMIR Analysis in ADE Using Spectre APS? It is recommended to start with the direct method and move to the iterated method after evaluating the accuracy of iterated and direct methods on the target design. The first method is the direct (default) method which provides SPICE-like accuracy by solving the entire circuit, including parasitics in Spectre APS. To cancel the current command, press ESC. %PDF-1.5 Spectre Tech Tips is a blog series aimed at exploring the capabilities and potential of Spectre. You can specify the options for EMIR analysis in the Analysis, Solver, and Options tabs, which build the content of the EMIR config file. Click on Setup-> Simulator/Directory/Host, choose spectre as the "Simulator" and click OK. 1. Figure 2 The V16 release has integrated Cadence's Clarity 3D Solver to handle complex EM simulation tasks in 5G, automotive, and high-performance computing (HPC) designs. ADE-XL(GXL) and ADE-Explorer(called as Maestro) are available in IC6 Virtuoso of Cadence. The following will step you through the process of starting up the Cadence tools. "-Online Course-, Jaikrishnan Mahalekshmi Sahasranamam, Arioso Systems, "Very, very good. In the Data View window, select Corners . In addition to providing insight into the useful features and enhancements in Spectre, this series broadcasts the voice of different bloggers and experts, who would share their knowledge and experience on all things related to Spectre. While Spectre performs the circuit simulation, calculates the IR drop and EM current values, and stores them in a binary database, Voltus-Fi XL evaluates the EM-related techfile information, compares the calculated currents with the current limits in the techfile, and visualizes the EMIR results in the layout editor. Option 1 Double click the parameter value Click the button on the right of the value Run simulation Option 2 Setup the parameter sweep in ADE L Save the setup to an .il file Load the saved .il file into ADE (G)XL parameter setup Run simulation Corner Simulations using ADE XL Regarding the optomizer, first time I hear that the adexl has an optimizer. Click Add new corner . xY[o~7XDk c'EE y%&,"7gYRRZMGfg>//WEx}%]|TBiq:?S"J8YT?~:?cv_Q6{z(mUqm@$j~ t497?} 9!k/Li"HzjmUT*Z(%c5-daDZ$2/Zg:2mv[AvIQ2j However monte-calro environment is available in both ADE-XL (GXL) and ADE-Explorer (called as Maestro). Thank you for this very good training. - Blended Course-, I am very grateful that these online videos are offered. You need to perform the following additional steps to set up EMIR analysis: The EMIR flow requires a DSPF file to be extracted for the block to be analyzed with EMIR. Virtuoso ADE Explorer and Assembler S4: Monte Carlo Analysis, Real-Time Tuning and Run Plans, Virtuoso ADE Explorer and Assembler S1: ADE Explorer and Single Test Corner Analysis, Virtuoso ADE Explorer and Assembler S2: ADE Assembler and Multi Test Corner Analysis, Virtuoso ADE Explorer and Assembler S3: Sweeping Variables and Simulating Corners, Cadence Cerebrus Intelligent Chip Explorer, Voltus-XFi Custom Power Integrity Solution, SI/PI Analysis Point Tools for IC Packaging, Advanced PCB Design & Analysis Resources Hub, Cadence Joint Enterprise Data and AI Platform, Custom IC / Analog / Microwave & RF Design Courses, Auto stop your Monte Carlo run based on target yield, Plot histograms and print statistical parameters, Edit your variables and parameters without affecting actual setup using the Real-Time Tuning assistant in the ADE Explorer, Run a single simulation and dynamically fine-tune results to see updated values, Create a mini run plan in the Run Plan assistant, Save the run plan as a batch script for regression runs, Monte Carlo Simulations in the ADE Explorer, Appendix A: Overview of Cadence Software (Optional), Appendix B: Performing Reliability Analysis (Optional). }^q"LvL ecwOZ J4f(dGf3(})#&=B* '}qr>_#&fa: 'C' )u4w-]}mh9*lZX[] q;@L@dr[ E6/Y5fPpSWLm}1}N4,e/q$6mqz4Vo0_7;a /d{Lr+:n6^L*W}^LFaYQcF^F 6&~5 F' M1$ pFCsAi+/. How to perform montecarlo simulat. You can simulate your design (schematic, extracted layout etc.) why it is used. bugcadence ic618 centos os7 VMware Workstation 16 Pro layoutDRCbug The following products could not be licensed sufficiently:- Calibre Interactive IC617 . In the ADE Explorer session, find the Design Variable "Length" in the Setup window on the left. Then depending on the technology you use, the model files will vary. Offering a full verification flow to our customers and partners that delivers the highest verification throughput in the industry. Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence package implementation products deliver the automation and accuracy. nucleare, tutorial cadence design environment web itu edu tr, virtuoso ade explorer cadence design systems, cadence allegro user manual neyrabeli files . In addition to the parasitic R and C elements, and devices, such as MOSFET and BJT, the DSPF file contains layer, coordinate, and width/length/area information, which is required for EMIR analysis. However, before including the DSPF file in the simulation, it is recommended that you run the spfchecker utility on the DSPF file to ensure that the DSPF file is free of errors. Verilog-A is a high-level language that uses modules to describe the structure and behavior of analog systems and their components. Browse Cadences latest on-demand sessions and upcoming events. Happy Reading! You also learn to format output data and to use waveform filters to improve simulation performance. Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence package implementation products deliver the automation and accuracy. 2 0 obj

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